1. Field of The Invention
The present invention relates to semiconductor memory devices, and more particularly to a high voltage switching circuit.
2. Background Art
For an EEPROM (Electrically Erasable Programmable Read Only Memory), a destructive voltage across a transistor is a serious problem caused by a high voltage produced in a memory integrated circuit when programming or erasing data.
A conventional high voltage switching circuit shown in FIG. 1 includes: a NAND gate 10 for buffering input signals; a depletion type transistor 12 having a channel connected between an output terminal of NAND gate 10 and a first node 11 for disconnecting a source voltage from a high voltage; and, a high voltage pumping circuit 14 connected between the first node 11 and an output terminal for producing either a high voltage or a ground voltage in response to the input signals. The high voltage pumping circuit 14 further includes: a first NMOS transistor 16 having a channel connected between a high voltage supply V.sub.pp and a second node 22, and further having a gate connected to the first node 11; a second NMOS transistor 18 having a channel connected between the first and second nodes 11 and 22, and, further having a gate connected to the second node 22, and a third NMOS transistor 30 having a gate connected to the second node 22 and a channel having both terminals commonly connected to each other.
In a high voltage switching operation, the input terminal is supplied with a high voltage V.sub.pp, a first input .PHI.D of NAND gate 10 is maintained in a high state, a gate input .PHI.P of depletion transistor 12 is in a low state, and an input .PHI. of the third NMOS transistor 30 makes periodic oscillations. In this case, if a second input of NAND gate 10 receives a signal having a high level, the output of NAND gate 10 is in a ground level and, therefore, so is first node 11.
However, if the second input of NAND gate 10 receives a signal having a low level, the output of NAND gate 10 is a high level. Depletion transistor 12 is turned on to provide the first node 11 with a voltage obtained by subtracting the threshold voltage of transistor 12 from the high level of NAND gate 10, thereby driving the high voltage pumping circuit 14. Also, depletion transistor 12 disconnects the output voltage of NAND gate 10 from the high voltage of first node 11. In this case, the gate of transistor 12 is provided with a ground voltage. If the gate of depletion transistor 12 is provided with a source voltage V.sub.cc, a short circuit operation occurs between high voltage supply V.sub.pp and source voltage V.sub.cc, so as not to produce a high voltage on the output terminal.
In a high voltage switching operation, a break-down voltage across depletion transistor 12 occurs due to an electric field between the gate and drain of depletion transistor 12 when the output terminal is raised to a high voltage and the gate of depletion transistor 12 is grounded. Hence, a high voltage at the output terminal may not be produced above a given value in order to prevent this problem. The problem can be resolved through the manufacturing process, however, the size of the semiconductor integrated circuit is unavoidably increased making it difficult to achieve a highly integrated circuit.